Albert-Jan N. Yzelman
What's new
- A revision on DAG Scheduling in the BSP Model has been made available (mirror). It now includes a proof that communication-aware multi-processor BSP scheduling of arbitrary DAGs is APX-hard.
- My text on Humble Heroes (citation) has left press. Humble here refers to the notion of the humble programmer, a concept first coined by Edsger Dijkstra, who urged us to approach programming while respecting the intrinsic limitations of the human mind. Today, few programming models are humble. Even fewer are both humble and scalable. Almost none are humble, scalable, and high performance.
The ever-increasing scale and complexity of computing systems – inspired by ever-increasing scales of problems and data – however, requires ever-more programmers, each with ever-deeper expertise, to write programs that require ever-higher scalability and performance.
In a bid to resolve this juxtaposition, Humble Heroes argues many humble programming models can be built on top of a few foundational ones, while retaining high performance and optimal scalability– and demonstrates this is feasible by introducing and evaluating ALP/Pregel, freely available on GitHub. - A brief announcement at SPAA '24 on multi-processor pebbling has just been published with the ACM. It presents a new model for parallel computation and some hardness and inapproximability results. These is an additional contribution to the full paper on scheduling in increasingly realistic models, also presented at SPAA '24 and previously presented at IPDPS '24 as a poster.
- Our paper Efficient Multi-Processor Scheduling in Increasingly Realistic Models has been accepted into SPAA 2024. It studies the problem of scheduling arbitrary (Hyper-)DAGs under parallel computer models that account for data movement costs over hierarchical memory architectures, considering both non-uniform memory access latencies as well as non-uniform memory throughputs. Our scheduling framework combines NUMA-aware heuristics with ILP formulations and ILP solvers, and finds schedules that achieve up to 2.5x lower cost compared to baselines. Even when limited to uniform memory latency and throughput, our framework achieves 24 to 44 percent smaller cost on average compared to baselines. This work will also be presented at IPDPS 2024 as a poster.
Contact info
Department: | Computing Systems Laboratory |
Postal: | Huawei Zürich Research Center Leonardo Thurgauerstrasse 80 8050 Zürich, Switzerland |
E-mail: | albertjan.<last name>@huawei.com |
albert-jan@<last name>.net | |
Telephone: | +41 7 6556 0 676 |
ORCID: | 0000-0001-8842-3689 |
Overview
- Publications
- Presentations
- ALP/Pregel & ALP/GraphBLAS (gitee), MulticoreBSP, and other software
- A short biography, and an even shorter one