Cache Simulator -- perfect cache simulator

Alpha

The cache simulator uses the CACHE, CS_ELEMENT, CS_ARRAY, CS_MATRIX, CS_CRS and CS_ICRS classes to simulate cache behaviour in order to obtain cache performance statistics.

This is not a trace-driven cache simulator. Applications simply use the classes provided by this library instead of normal datatypes.

This library is developed as a means to obtain cache hit/miss statistics in the area of sparse matrix operations, using our own idealised cache model:

-The cache is k-way set-associative cache.

-There is only one cache in between the CPU and main memory; i.e., we assume a single-level cache architecture.

-The cache is always full; that is, cache lines always store valid data. Hence a cache miss always results in a cache eviction.

-The replacement policy when choosing between $k$ cache lines is the Least Recently Used (LRU) policy.

-Reading in n cache lines from main memory to the cache takes O(l_m+nb_m) time, where l_m,b_m in (0,infinity) constant.

-Reading in n cache lines from cache to CPU takes O(l_c+nb_c) time, where l_c,b_c in (0,infinity) constant.

-Analogously: writing n cache lines from CPU to cache takes O(l_c+nb_c) time, whereas writing from cache to main memory takes O(l_m+nb_m) time.

The current framework only keeps statistics on the number of cache hits and misses.

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